Digital Staff Engineer

؜ - ؜القاهرة ؜ -

تفاصيل الوظيفة


  • Develop a thorough understanding of system-level design specifications

  • Derive top-level digital architecture planning

  • Verilog RTL Coding, Synthesis, Simulation of the digital IPs

  • Working with the verification team to develop advanced test plans

  • Oversee static timing analysis and timing closure

  • Hardware verification of the digital module using cutting edge FPGA kits

  • Manage support of customer applications and use-cases

  • Contribute to the validation and debugging of the fabricated silicon
    Job Requirements

  • B.Sc. or M.Sc. in Electronics Engineering

  • ‎5+ Years of experience in VLSI Digital Design

  • Technical leadership and project management skills

  • Excellent verbal and written communication skills are required

  • Excellent follow-up and persistence

  • Strong technical judgement and decision making abilities

  • Expert knowledge in Verilog RTL coding techniques

  • Strong Knowledge of ASIC/FPGA design flows including RTL synthesis, and timing closure of high speed digital designs

  • Experience with clock domain crossing and reset architecture

  • Knowledge of System Verilog, RTL/gate verification techniques

  • Strong knowledge of Shell, Perl, Python and TCL scripting

  • Strong knowledge of Unix/Linux operating system

ملخص الوظيفة

  • المُعلن : Mixel
  • تاريخ الإعلان : 08/11/2022
  • نوع العمل : -
  • مستوى الخبرة : -
  • المستوى التعليمي : -
  • مكان العمل : القاهرة
  • الراتب : -
  • الهاتف : -

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